1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a nonvolatile memory device with a three-dimensional structure and a method for operating the same.
2. Description of the Related Art
A nonvolatile memory device retains stored data even when power is interrupted. Two-dimensional (2D) memory devices fabricated in a single layer on a silicon substrate have limitations in improving integration density. Therefore, 3D nonvolatile memory devices with memory cells stacked vertically from a silicon substrate have been proposed.
In general, in a nonvolatile memory device, a program/erase operation is performed using an F-N (Fowler-Nordheim) tunneling phenomenon. The F-N tunneling involves electrons that move through a tunnel dielectric layer between a floating gate and a channel by inducing a high potential difference between the floating gate and the channel. For example, a program operation is performed by transferring a program voltage (a high voltage) to a floating gate so that the electrons of a channel are implanted into the conductive band of the floating gate, and conversely, an erase operation is performed by transferring an erase voltage (a high voltage) to the channel so that the electrons implanted into the conductive band of the floating gate are discharged into the channel. In a nonvolatile memory device with a two-dimensional structure, an erase voltage is applied to a bulk formed in a substrate to be transferred to a channel, and an erase operation is performed by a unit of a block.
However, unlike the nonvolatile memory device with a two-dimensional structure, in a nonvolatile memory device with a three-dimensional structure, the speed of the erase operation and boosting of the potential of a channel may decrease. In the nonvolatile memory device with a three-dimensional structure, applying an erase bias due to the structure of the nonvolatile memory device may be difficult. More specifically, in a conventional nonvolatile memory device with a two-dimensional structure, since respective memory cells are formed in a substrate, the erase operation can be performed by applying an erase bias to the bulk of the substrate. Conversely, in a nonvolatile memory device with a three-dimensional structure, since memory cells are stacked along a channel extending from a substrate to define the three-dimensional structure, an erase bias may be difficult to transfer to a channel for an erase operation.
Therefore, in the nonvolatile memory device with a three-dimensional structure, an erase operation may be performed using GIDL (gate induced drain leakage) current.
FIG. 1 is a view illustrating the generation of GIDL current. For illustration purposes, gates and drains are mainly illustrated.
When a gate-to-drain junction overlap exists, as indicated by the reference symbol ‘O’, if a high voltage is applied to a gate electrode, GIDL current is generated due to direct tunneling between the gate electrode and a drain region. For the smooth generation of this GIDL current, a doping formation including a doping density difference that abruptly changes at the junction of a GIDL current inducing portion may be included.
Such GIDL current is utilized in the erase operation of the nonvolatile memory device with a three-dimensional structure. In detail, the nonvolatile memory device with a three-dimensional structure includes a channel that extends vertically, a source selection transistor, a plurality of memory cells, which are vertically stacked along the channel, a drain selection transistor, which is vertically stacked along the channel, and a source line and a bit line, which are respectively connected to both ends of the channel. In particular, for the generation of GIDL current, high density N-type impurity doping regions are provided on both ends of the channel, more specifically, on the channel portion between the source selection transistor and the source line and/or on the channel portion between the drain selection transistor and the bit line. In this structure, if a high voltage is applied to the gate of the source selection transistor or the drain selection transistor, the GIDL current may be generated. The hot holes generated by the GIDL current are supplied to the channel and are used in an erase operation.
Nevertheless, in such an erase operation, since the rate of the hot holes generated by the GIDL current is low, the speed of the erase operation is low. Also, while optimizing the doping density of the N-type impurity doping regions formed on both ends of the channel may be useful to ensure the smooth generation of the GIDL current in the three-dimensional structure because the channel is formed using polysilicon with a high impurity diffusion speed, optimizing the doping density may be difficult.